FPGA Noise Cancellation: A remote DSP lab in Verilog

I turned a DE2i-150 FPGA board with an audio codec card into a digital signal processing lab that runs completely remotely. A script picks a signal source (a sine wave, white noise, clicks or the microphone), routes it through DSP blocks I wrote in Verilog, records the result in on-chip memory and downloads it over JTAG for analysis.

The blocks include a 63-tap low-pass FIR filter, an LMS adaptive filter and full FxLMS active noise cancellation, the algorithm used in noise-cancelling headphones. Every block was checked in simulation first, then measured on the hardware: the filter's measured response stays within 2 dB of its design, and the stopband is more than 50 dB down.

In a simulated room built into the FPGA, the noise cancellation drives the noise at the error microphone down by 50 dB in about 160 ms, matching the simulation to a fraction of a decibel. Later versions added step-size normalisation and leakage for robustness, and a multichannel engine with two speakers and two microphones, switchable at runtime between the virtual room and real speakers and microphones. A small web console and a live scope let me run experiments from a browser.